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| 19-0774; Rev 1; 7/09 KIT ATION EVALU E AILABL AV 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch General Description The MAX2830 direct conversion, zero-IF, RF transceiver is designed specifically for 2.4GHz to 2.5GHz 802.11g/b WLAN applications. The MAX2830 completely integrates all circuitry required to implement the RF transceiver function, providing an RF power amplifier (PA), an Rx/Tx and antenna diversity switch, RF-to-baseband receive path, baseband-to-RF transmit path, voltage-controlled oscillator (VCO), frequency synthesizer, crystal oscillator, and baseband/control interface. The MAX2830 includes a fast-settling sigma-delta RF synthesizer with smaller than 20Hz frequency steps and a digitally tuned crystal oscillator allowing use of a low-cost crystal. No I/Q calibration is required; however, the device also integrates on-chip DC-offset cancellation and I/Q errors and carrier leakage-detection circuits for improved performance. Only an RF bandpass filter (BPF), crystal, a pair of baluns, and a small number of passive components are needed to form a complete 802.11g/b WLAN RF frontend solution. The MAX2830 completely eliminates the need for an external SAW filter by implementing on-chip monolithic filters for both the receiver and transmitter. The baseband filters are optimized to meet the IEEE 802.11g standard and proprietary turbo modes up to 40MHz channel bandwidth. These devices are suitable for the full range of 802.11g OFDM data rates (6Mbps to 54Mbps) and 802.11b QPSK and CCK data rates (1Mbps to 11Mbps). The ICs are available in a small, 48-pin thin QFN package measuring only 7mm x 7mm x 0.8mm. Features 2.4GHz to 2.5GHz ISM Band Operation IEEE 802.11g/b Compatible (54Mbps OFDM and 11Mbps CCK) Complete RF Transceiver, PA, Rx/Tx and Antenna Diversity Switch, and Crystal Oscillator Best-in-Class Transceiver Performance 62mA Receiver Current 3.3dB Rx Noise Figure -75dBm Rx Sensitivity (54Mbps OFDM) No I/Q Calibration Required 0.1dB/0.35 Rx I/Q Gain/Phase Imbalance 33dB RF and 62dB Baseband Gain Control Range 60dB Range Analog RSSI per RF Gain Setting Fast Rx I/Q DC-Offset Settling Programmable Baseband Lowpass Filter 20-Bit Sigma-Delta Fractional-N PLL with < 20Hz Step Size Digitally Tuned Crystal Oscillator +17.1dBm Transmit Power (5.6% EVM with 54Mbps OFDM) 31dB Tx Gain Control Range Integrated Power Detector Fully Integrated RF Input and Output Matching and DC Blocking Serial or Parallel Gain-Control Interface > 40dB Tx Sideband Suppression Without Calibration Rx/Tx I/Q Error Detection Transceiver Operates from +2.7V to +3.6V PA Operates from +2.7V to +4.2V Low-Power Shutdown Mode Small 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm) MAX2830 Applications Wi-Fi, PDA, VOIP, and Cellular Handsets Wireless Speakers and Headphones General 2.4GHz ISM Radios Selector Guide PART MAX2830 MAX2831 MAX2832 INTEGRATED PA Yes Yes No INTEGRATED SWITCH Yes No No PART MAX2830ETM+T Ordering Information TEMP RANGE -40C to +85C PIN-PACKAGE 48 TQFN-EP* *EP = Exposed paddle. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 ABSOLUTE MAXIMUM RATINGS VCCTXPA, VCCPA, and ANT_ _ to GND ..................-0.3V to +4.5V VCCLNA, VCCTXMX, VCCPLL, VCCCP, VCCXTAL, VCCVCO, VCCRXVGA, VCCRXFL, and VCCRXMX_ to GND...-0.3V to +3.9V B6, B7, B3, B2, SHDN, B5, CS, SCLK, DIN, B1, TUNE, B4, ANTSEL, TXBBI_, TXBBQ_, RXHP, RXTX, RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT, XTAL, CTUNE to GND ....................-0.3V to (Operating VCC + 0.3V) RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT Short-Circuit Duration .........................................................10s RF Input Power ...............................................................+10dBm Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN (derates 27.8mW/C above +70C)....2.22W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (MAX2830 EV kit, VCC_ = 2.7V to 3.6V, VCCPA = VCCTXPA = 2.7V to 4.2V, TA = -40C to +85C, Rx set to the maximum gain. CS = high, RXHP = SCLK = DIN = ANTSEL = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs terminated into 50, receiver baseband outputs are open. 100mVRMS differential I and Q signals (54Mbps IEEE 802.11g OFDM) applied to I/Q baseband inputs of transmitter in transmit mode, fREF = 40MHz, and registers set to recommended settings and corresponding test mode, unless otherwise noted. Typical values are at VCC = 2.8V, VCCPA = 3.3V, and TA = +25C, LO frequency = 2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETERS Supply Voltage VCC_ VCCPA, VCCTXPA Shutdown mode, B7: B1 = 0000000, reference oscillator not applied Standby mode Supply Current Rx mode Tx mode, TA = +25C, VCC = 2.8V, VCCPA = 3.3V (Note 2) Rx calibration mode Tx calibration mode Rx I/Q Output Common-Mode Voltage Rx I/Q Output Common-Mode Voltage Variation Tx Baseband Input CommonMode Voltage Operating Range Tx Baseband Input Bias Current TA = +25C TA = -40C (relative to TA = +25C) TA = +85C (relative to TA = +25C) DC-coupled Source current 0.9 CONDITIONS MIN 2.7 2.7 TYP MAX 3.6 4.2 UNITS V TA = +25C 20 A TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C Transmit section PA, POUT = +17.1dBm TA = +25C TA = +25C 0.94 28 62 35 35 78 82 mA 82 212 101 78 1.2 -17 15 104 1.37 V mV 1.3 22 V A 2 _______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch DC ELECTRICAL CHARACTERISTICS (continued) (MAX2830 EV kit, VCC_ = 2.7V to 3.6V, VCCPA = VCCTXPA = 2.7V to 4.2V, TA = -40C to +85C, Rx set to the maximum gain. CS = high, RXHP = SCLK = DIN = ANTSEL = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs terminated into 50, receiver baseband outputs are open. 100mVRMS differential I and Q signals (54Mbps IEEE 802.11g OFDM) applied to I/Q baseband inputs of transmitter in transmit mode, fREF = 40MHz, and registers set to recommended settings and corresponding test mode, unless otherwise noted. Typical values are at VCC = 2.8V, VCCPA = 3.3V, and TA = +25C, LO frequency = 2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETERS CONDITIONS MIN VCC 0.4 0.4 -1 -1 VCC 0.4 0.4 +1 +1 TYP MAX UNITS LOGIC INPUTS: SHDN, RXTX, SCLK, DIN, CS, B7:B1, RXHP, ANTSEL Digital Input-Voltage High, VIH Digital Input-Voltage Low, VIL Digital Input-Current High, IIH Digital Input-Current Low, IIL LOGIC OUTPUTS: LD, CLOCKOUT Digital Output-Voltage High, VOH Digital Output-Voltage Low, VOL Sourcing 100A Sinking 100A V V V V A A MAX2830 AC ELECTRICAL CHARACTERISTICS--Rx Mode (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER RF Input Frequency Range High RF gain RF Input Return Loss (ANT1) Mid RF gain Low RF gain High RF gain RF Input Return Loss (ANT2) Mid RF gain Low RF gain Maximum gain, B7:B1 = 1111111 Total Voltage Gain (ANT1) Minimum gain, B7:B1 = 0000000 Maximum gain, B7:B1 = 1111111 Total Voltage Gain (ANT2) Minimum gain, B7:B1 = 0000000 TA = +25C 2 TA = +25C TA = -40C to +85C TA = +25C TA = +25C 86 83 2 96 dB 8 CONDITIONS MIN 2.4 13 16 13 21 14 12 97 dB dB dB TYP MAX 2.5 UNITS GHz RECEIVER SECTION: LNA RF INPUT-TO-BASEBAND I/Q OUTPUTS _______________________________________________________________________________________ 3 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 AC ELECTRICAL CHARACTERISTICS--Rx Mode (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER CONDITIONS From high-gain mode (B7:B6 = 11) to medium-gain mode (B7:B6 = 10) RF Gain Steps (Note 3) From high-gain mode (B7:B6 = 11) to low-gain mode (B7:B6 = 0X) RF Gain-Change Settling Time Gain change from high gain to medium gain, high gain to low, or medium gain to low gain; gain settling to within 2dB of steady state; RXHP = 1 From maximum baseband gain (B5:B1 = 11111) to minimum baseband gain (B5:B1 = 00000) Voltage gain = maximum with B7:B6 = 11 DSB Noise Figure (ANT1) Voltage gain = 50dB with B7:B6 = 11 Voltage gain = 45dB with B7:B6 = 10 Voltage gain = 15dB with B7:B6 = 0X Voltage gain = maximum with B7:B6 = 11 DSB Noise Figure (ANT2) Voltage gain = 50dB with B7:B6 = 11 Voltage gain = 45dB with B7:B6 = 10 Voltage gain = 15dB with B7:B6 = 0X B7:B6 = 11 -19dBVRMS baseband output EVM degrades to 9% B7:B6 = 11 Out-of-Band Input IP3 (Note 4) I/Q Phase Error I/Q Gain Imbalance RX I/Q Output Load Impedance (R || C) Tx-to-Rx Conversion Gain for Rx I/Q Calibration Baseband VGA Settling Time I/Q Output DC Step when RXHP Transitions from 1 to 0 in Presence of 802.11g Short Sequence B7:B6 = 10 B7:B6 = 0X 1 variation (without calibration) 1 variation (without calibration) Minimum differential resistance Maximum differential capacitance For receiver gain, B7:B1 = 1101111 (Note 5) Gain change from B5:B1 = 10111 to B5:B1 = 00111; gain settling to within 2dB of steady state After switching RXHP to logic 0 from initial logic 1, during ideal short sequence data at -55dBm input in AWGN channel, for -19dBV output; normalized to RMS signal on I and Q outputs; transition point varied from 0 to 0.8s in steps of 0.1s B7:B6 = 10 B7:B6 = 0X 54 -33.5 MIN TYP -17 dB MAX UNITS 0.2 s Baseband Gain Range 62 3.3 3.8 16.7 34.7 4.0 4.5 17.4 35.3 -41 -24 -6 2.5 -12 -4 24 0.35 0.1 10 10 0.5 0.1 68 dB dB dB In-Band Compression Point Based on EVM In-Band Output P-1dB dBm VP-P dBm Degrees dB k pF dB s Voltage gain = 90dB, with B7:B6 = 11 -5 dBc 4 _______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch AC ELECTRICAL CHARACTERISTICS--Rx Mode (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications that normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER I/Q Output DC Droop I/Q Static DC Offset Spurious Signal Emissions from LNA input CONDITIONS After switching RXHP to 0, D13:D12, Register 7 (A3:A0 = 0111) RXHP = 1, B7:B1 = 1101110, 1 variation RF = 1GHz to 26.5GHz ANT1 to receiver (in ANT2 mode) ANT to Receiver Isolation ANT2 to receiver (in ANT1 mode) RECEIVER BASEBAND FILTERS Gain Ripple in Passband Group-Delay Ripple in Passband Baseband Filter Rejection (Nominal Mode) RSSI RSSI Minimum Output Voltage RSSI Maximum Output Voltage RSSI Slope RSSI Output Settling Time To within 3dB of steady state +32dB signal step -32dB signal step RLOAD 10k || 5pF RLOAD 10k || 5pF 0.4 2.4 30 200 600 V V mV/dB ns 10kHz to 8.5MHz at baseband 10kHz to 8.5MHz at baseband At 8.5MHz At 15MHz At 20MHz At > 40MHz 1.3 45 3.2 27 50 80 dB dBP-P nsP-P 47 MIN TYP 1 1 -51 20 dB MAX UNITS V/s mV dBm MAX2830 _______________________________________________________________________________________ 5 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 AC ELECTRICAL CHARACTERISTICS--Tx Mode (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fRF = 2.439GHz , fLO = 2.437GHz. fREF = 40MHz, SHDN = RXTX = CS = ANTSEL = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications circuit. 100mVRMS sine and cosine signal (or 100mVRMS 54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER RF Output Frequency Range 54Mbps 802.11g OFDM signal Output Power 6Mbits, OFDM, I/Q signals Gain Control Range Carrier Leakage at Center Frequency of Channel B6:B1 = 000000 to 111000 Output power adjusted to meet 5.6%EVM, and spectral mask Output power adjusted to meet spectral mask CONDITIONS MIN 2.4 17.1 dBm 20.3 26 -42 -30 -67 -36 -47 -64 -42 -65 -55 -27 -54 -15 20 0.7 Nominal mode 11 62 0.35 1.2 0.3 dB k pF MHz dB V V s dBm/ MHz dB dBc dBc TYP MAX 2.5 UNITS GHz TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS Unwanted Sideband Suppression Without I/Q calibration, B6:B1 = 100001 Without DC offset correction 1/3 x fLO < 1GHz > 1GHz Transmitter Spurious Signal Emissions B6:B1 = 111000, OFDM signal 2/3 x fLO 4/3 x fLO 5/3 x fLO 8/3 x fLO 2 x fLO 3 x fLO RF Output Return Loss Tx I/Q Input Load Impedance (R || C) Baseband -3dB Corner Frequency Baseband Filter Rejection Minimum Power-Detector Output Voltage Maximum Power-Detector Output Voltage RF Power-Detector Response Time Off-chip balun and single ended Minimum differential resistance Maximum differential capacitance D1:D0 = 01, Register 8 (A3:A0 = 1000) At 30MHz, in nominal mode Short sequence transmitter power = +10dBm Short sequence transmitter power = +20dBm 6 _______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch AC ELECTRICAL CHARACTERISTICS--Tx Mode (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fRF = 2.439GHz , fLO = 2.437GHz. fREF = 40MHz, SHDN = RXTX = CS = ANTSEL = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications circuit. 100mVRMS sine and cosine signal (or 100mVRMS 54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS MAX2830 TRANSMITTER LO LEAKAGE AND I/Q CALIBRATION USING LO LEAKAGE AND SIDEBAND DETECTOR (see the Rx/Tx Calibration Mode section) Tx BASEBAND I/Q INPUTS TO RECEIVER OUTPUTS Output at 1 x fTONE (for LO leakage = -29dBc), fTONE = 2MHz, 100mVRMS Output at 2 x fTONE (for LO leakage = -240dBc), fTONE = 2MHz, 100mVRMS -34 dBVRMS -44 30 1 dB MHz LO Leakage and Sideband Detector Output Calibration register, D12:D11 = 00, A3:A0 = 0110 Amplifier Gain Range Lower -3dB Corner Frequency D12:D11 = 00 to D12:D11 = 11, A3:A0 = 0110 _______________________________________________________________________________________ 7 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 AC ELECTRICAL CHARACTERISTICS--Frequency Synthesizer (MAX2830 EV kit, VCC_ = 2.7V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER FREQUENCY SYNTHESIZER RF Channel Center Frequency Channel Center Frequency Programming Minimum Step Size Charge-Pump Comparison Frequency Reference Frequency Range Reference Frequency Input Levels Reference Frequency Input Impedance (R || C) AC-coupled to XTAL pin Resistance (XTAL) Capacitance (XTAL) fOFFSET = 1kHz fOFFSET = 10kHz Closed-Loop Phase Noise fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET = 10MHz Closed-Loop Integrated Phase Noise Charge-Pump Output Current Reference Spurs VCO Frequency Error 20MHz offset Measured from Tx-Rx or Rx-Tx transition 3s to 9s > 9s RMS phase jitter; integrate from 10kHz to 10MHz offset 20 800 5 4 -86 -94 -94 -110 -120 0.9 1 -55 50 1 210 103 86 Degrees mA dBc kHz dBc/Hz 2.4 20 2.5 GHz Hz CONDITIONS MIN TYP MAX UNITS 20 44 MHz MHz mVP-P k pF VOLTAGE-CONTROLLED OSCILLATOR Pushing LO Tuning Gain Referred to 2400MHz LO, VCC varies by 0.3V VTUNE = 0.5V VTUNE = 2.2V kHz MHz/V 8 _______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch AC ELECTRICAL CHARACTERISTICS--Miscellaneous Blocks (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, fLO = 2.437GHZ, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER CRYSTAL OSCILLATOR On-Chip Tuning Capacitance Range On-Chip Tuning Capacitance Step Size ON-CHIP TEMPERATURE SENSOR TA = -40C Output Voltage A3:A0 = 1000, D9:D8 = 01 TA = +25C TA = +85C 0.35 1 1.6 V Maximum capacitance, A3:A0 = 1110, D6:D0 = 1111111 Minimum capacitance, A3:A0 = 1110, D6:D0 = 0000000 15.4 0.5 0.12 pF pF CONDITIONS MIN TYP MAX UNITS MAX2830 AC ELECTRICAL CHARACTERISTICS--Timing (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYSTEM TIMING (see Figure 3) Turn-On Time Crystal Oscillator Turn-On Time Channel Switching Time From SHDN rising edge to LO settled within 1kHz using external reference frequency input 90% of final output amplitude level Loop BW = 150kHz, fRF = 2.5GHz to 2.4GHz Measured from Tx or Rx enable rising edge; signal settling to within 2dB of steady state Rx to Tx Tx to Rx, RXHP = 1 60 1 25 2 s 2 1.5 1 1.9 0.1 s s s s s ms s CONDITIONS MIN TYP MAX UNITS Rx/Tx Turnaround Time Tx Turn-On Time (from Standby Mode) Tx Turn-Off Time (from Standby Mode) Rx Turn-On Time (from Standby Mode) Rx Turn-Off Time (from Standby Mode) From Tx-enable active rising edge; signal settling to within 2dB of steady state From Tx-enable inactive rising edge From Rx-enable active rising edge; signal settling to within 2dB of steady state From Rx-enable inactive rising edge _______________________________________________________________________________________ 9 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 AC ELECTRICAL CHARACTERISTICS--Timing (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25C, unless otherwise noted.) (Note 1) PARAMETER 3-WIRE SERIAL-INTERFACE TIMING (see Figure 2) SCLK Rising Edge to CS Falling Edge Wait Time, tCSO Falling Edge of CS to Rising Edge of First SCLK Time, tCSS DIN to SCLK Setup Time, tDS DIN to SCLK Hold Time, tDH SCLK Pulse-Width High, tCH SCLK Pulse-Width Low, tCL Last Rising Edge of SCLK to Rising Edge of CS or Clock to Load Enable Setup Time, tCSH CS High Pulse Width, tCSW Time Between the Rising Edge of CS and the Next Rising Edge of SCLK, tCS1 Clock Frequency, fCLK Rise Time, tR Fall Time, tF 6 6 6 6 6 6 6 20 6 20 2 2 ns ns ns ns ns ns ns ns ns MHz ns ns CONDITIONS MIN TYP MAX UNITS Note 1: Min and max limits are guaranteed by test above TA = +25C and guaranteed by design and characterization at TA = -40C. The power-on register settings are not production tested. Recommended register setting must be loaded after VCC is supplied. Note 2: Guaranteed by design and characterization. Note 3: The nominal part-to-part variation of the RF gain step is 1dB. Note 4: Two tones at +25MHz and +48MHz offset with -35dBm/tone. Measure IM3 at 2MHz. Note 5: Tx I/Q inputs = 100mVRMS. 10 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Typical Operating Characteristics (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Rx ICC vs. VCC MAX2830 toc01 MAX2830 NOISE FIGURE vs. BASEBAND GAIN SETTINGS MAX2830 toc02 Rx VOLTAGE GAIN vs. BASEBAND GAIN SETTING 90 80 70 LNA = HIGH GAIN MAX2830 toc03 67 66 TA = +85C 65 ICC (mA) 64 63 62 61 TA = -40C TA = +25C 45 40 35 30 NF (dB) 25 20 15 10 5 0 LNA = HIGH GAIN LNA = MEDIUM GAIN LNA = LOW GAIN 100 GAIN (dB) 60 50 40 30 20 10 0 LNA = LOW GAIN 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 GAIN SETTINGS LNA = MEDIUM GAIN 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 GAIN SETTINGS Rx IN-BAND OUTPUT P - 1dB vs. GAIN MAX2830 toc04 Rx EVM vs. PIN 20 18 16 14 EVM (%) 12 10 8 6 4 2 0 0 -80 -70 -60 -50 -40 -30 PIN (dBm) -20 -10 0 0.5 EVM (%) 2.0 1.5 1.0 LNA = HIGH GAIN LNA = MEDIUM GAIN LNA = LOW GAIN MAX2830 toc05 Rx EVM vs. VOUT PIN = -50dBm LNA = HIGH GAIN MAX2830 toc06 0 -1 OUTPUT P - 1dB (dBVRMS) -2 -3 -4 -5 -6 -7 15 25 35 45 55 65 GAIN (dB) 75 85 LNA MEDIUM/LOWGAIN SWITCH POINT LNA MEDIUM/HIGHGAIN SWITCH POINT 22 3.0 2.5 95 -29 -27 -25 -23 -21 -19 -17 -15 -13 -11 -9 VOUT (dBVRMS) OFDM EVM WITH OFDM JAMMER vs. OFFSET FREQUENCY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -65 PIN = -62dBm fOFFSET = 20MHz MAX2830 toc07 Rx EMISSION SPECTRUM, LNA INPUT -50 -60 16/3 LO 20/3 LO 4/3 LO 2 LO 8/3 LO INPUT RETURN LOSS (dB) -70 -80 dBm 4 LO -10 MAX2830 toc08 LNA INPUT RETURN LOSS vs. RF FREQUENCY (ANT 1) MAX2830 toc09 -5 HIGH GAIN -15 EVM (%) fOFFSET = 25MHz -90 -100 -110 -120 -130 fOFFSET = 40MHz -140 -150 -20 MID GAIN LOW GAIN -25 DC 26.5GHz 2300 2400 2500 RF FREQUENCY (MHz) 2600 -55 -45 PJAMMER (dBm) -35 -25 ______________________________________________________________________________________ 11 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Typical Operating Characteristics (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) LNA INPUT RETURN LOSS vs. RF FREQUENCY (ANT 2) MAX2830 toc09a Rx RSSI OUTPUT vs. INPUT POWER LNA = HIGH GAIN 2.5 RSSI OUTPUT (V) 2.0 1.5 1.0 0.5 0 LNA = LOW GAIN 0.45 -120 -100 -80 -60 -40 PIN (dBm) -20 0 20 LNA = MEDIUM GAIN 0 1.45V MAX2830 toc10 Rx RSSI STEP RESPONSE (+32dB LNA GAIN STEP) MAX2830 toc11 -5 LOW GAIN INPUT RETURN LOSS (dB) -10 3.0 3V -15 -20 HIGH GAIN -25 2300 2350 2400 2450 2500 RF FREQUENCY (MHz) 2550 2600 MID GAIN 200ns/div Rx RSSI STEP RESPONSE (-32dB LNA GAIN STEP) MAX2830 toc12 Rx I/Q DC OFFSET SETTLING RESPONSE (+8dB BB VGA GAIN STEP) MAX2830 toc13 Rx I/Q DC OFFSET SETTLING RESPONSE (-8dB BB VGA GAIN STEP) MAX2830 toc14 3V 2.0V 2.5V 0V 1.5V 0V 10mV 5mV 0V 0V 10mV 5mV 0mV 40ns/div 40ns/div 0V 200ns/div Rx I/Q DC OFFSET SETTLING RESPONSE (-16dB BB VGA GAIN STEP) MAX2830 toc15 Rx I/Q DC OFFSET SETTLING RESPONSE (-32dB BB VGA GAIN STEP) MAX2830 toc16 I/Q OUTPUT DC ERROR DROOP (RxHP = 10; 100Hz MODE) MAX2830 toc17 3V 3V 3V 0V 0V 0V 0V 10mV 5mV 0V 400ns/div 10mV 5mV 0V 400ns/div -5mV -10mV 20ms/div 12 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Typical Operating Characteristics (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Rx BB VGA SETTLING RESPONSE (+8 GAIN STEP) MAX2830 toc18 MAX2830 Rx BB VGA SETTLING RESPONSE (-8 GAIN STEP) MAX2830 toc19 Rx BB VGA SETTLING RESPONSE (-16 GAIN STEP) MAX2830 toc20 3V 3V 3V 0V 500mV 0V -500mV 0V 500mV 0V -500mV 0V 500mV 0V -500mV 40ns/div 40ns/div 40ns/div Rx BB VGA SETTLING RESPONSE (-32 GAIN STEP) MAX2830 toc21 RF LNA SETTLING RESPONSE (HIGH TO MEDIUM) MAX2830 toc22 RF LNA SETTLING RESPONSE (HIGH TO LOW) MAX2830 toc23 3V 3V 3V 0V 500mV 0V -500mV 0V 500mV 0V -500mV 100ns/div 0V 500mV 0V -500mV 100ns/div 40ns/div Rx BB FREQUENCY RESPONSE vs. FINE SETTING (COARSE SETTING = 8.5MHz) MAX2830 toc24 Rx BB FREQUENCY RESPONSE vs. COARSE SETTING (FINE SETTING = 010) MAX2830 toc25 Rx BASEBAND FILTER GROUP DELAY MAX2830 toc26 20 0 -20 dB -40 -60 -80 -100 1 10 FREQUENCY (MHz) 20 0 -20 -40 dB -60 -80 -100 -120 20ns/div 1 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 12 ______________________________________________________________________________________ 13 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Typical Operating Characteristics (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) HISTOGRAM: Rx STATIC DC OFFSET MAX2830 toc27 HISTOGRAM: Rx GAIN IMBALANCE MAX2830 toc28 HISTOGRAM: Rx PHASE IMBALANCE MEAN: 0.3 STD: 0.314 SAMPLE SIZE: 1013 MAX2830 toc29 78 65 52 39 26 13 0 1/div MEAN: 0mV STD: 0.977mV SAMPLE SIZE: 1006 138 115 92 69 46 23 0 1/div MEAN: 0dB STD: 0.064dB SAMPLE SIZE: 951 114 95 76 57 38 19 0 1/div Tx ICC vs. VCC MAX2830 toc30 HISTOGRAM: Tx LO LEAKAGE MAX2830 toc31 HISTOGRAM: Tx SIDEBAND SUPPRESSION MEAN: -42dBc STD: 1.9dB SAMPLE SIZE: 1000 MAX2830 toc32 88 TA = +85C 86 TA = +25C ICC (mA) 84 48 40 32 24 MEAN: -33.45dBc STD: 6.31dB SAMPLE SIZE: 999 72 60 48 36 24 12 0 82 16 80 TA = -40C 8 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) 1/div 78 1/div Tx BASEBAND FILTER RESPONSE MAX2830 toc33 Tx EVM vs. POUT MAX2830 toc34 -10 FILTER RESPONSE (dB) -20 -30 -40 -50 -60 -70 -80 -90 0.1 1 10 16 14 12 EVM (%) 10 8 6 4 2 0 VCC = 4.2V 0 5 10 15 POUT (dBm) 20 VCC = 2.7V VCC = 3V VCC = 3.3V 330 PA SUPPLY CURRENT (mA) 300 270 240 210 180 150 VCCPA = 2.7V, 3.0V, 3.3V 0 5 10 15 POUT (dBm) 20 VCCPA = 4.2V 100 25 120 25 BASEBAND FREQUENCY (MHz) 14 ______________________________________________________________________________________ MAX2830 toc35 0 18 PA SUPPLY CURRENT vs. POUT 360 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Typical Operating Characteristics (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Tx GAIN VARIATION vs. FREQUENCY (B6:B1 = 101001) MAX2830 toc36 MAX2830 Tx OUTPUT POWER vs. FREQUENCY MAX2830 toc37 TRANSMIT EMISSION MASK POUT = +17.1dBm EVM = 5.6% MAX2830 toc38 18.0 GAIN ADJUSTED TO ACHIEVE 5.6% EVM 17.5 17.0 POUT (dBm) TA = -40C 2dB/div TA = +25C 16.5 16.0 15.5 15.0 TA = -40C TA = +85C 2.4 2.42 2.44 2.46 FREQUENCY (GHz) 2.48 2.5 2.40 2.42 2.44 2.46 FREQUENCY (GHz) 2.48 2.50 10dB/div 2387 TA = +25C TA = +85C 2407 2427 2447 2467 2487 FREQUENCY/MHz 802.11g POUT vs. GAIN SETTING (UPPER GAIN CONTROL RANGE) MAX2830 toc39 POWER DETECTOR OVER FREQUENCY MAX2830 toc40 POWER DETECTOR OVER SUPPLY VOLTAGE VCCPA = 2.7V, 3.0V POWER DETECTOR (V) 1.5 MAX2830 toc41 22 2.5 2.0 POWER DETECTOR (V) 20 POUT (dBm) 2.0 fRF = 2.4GHz 1.5 18 1.0 1.0 fRF = 2.5GHz 16 0.5 VCCPA = 3.3V, 4.2V 0 0.5 14 40 44 48 52 56 GAIN SETTINGS 60 64 0 0 5 10 15 POUT (dBm) 20 25 0 5 10 15 POUT (dBm) 20 25 POWER DETECTOR OVER TEMPERATURE MAX2830 toc42 POWER-DETECTOR OUTPUT 300mV 20dB GAIN STEP PA ENVELOPE MAX2830 toc43 PA OUTPUT ENVELOPE RESPONSE 50mV MAX2830 toc44 2.5 2.0 POWER DETECTOR (V) TA = +85C -50mV 1.5 -300mV 1.0 TA = +25C, -40C 1V POWER DETECTOR 0.5 0V 0 0 5 10 15 POUT (dBm) 20 25 100ns/div 1s/div 20dBm 0 -20dBm PA ENVELOPE TX I/Q INPUT ______________________________________________________________________________________ 15 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Typical Operating Characteristics (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) PA OUTPUT RETURN LOSS vs. RF FREQUENCY MAX2830 toc45 Tx OUTPUT SPURS 10 LO 0 -10 -20 4 LO 3 MAX2830 toc46 LO FREQUENCY vs. VTUNE MAX2830 toc47 -10 2600 2550 OUTPUT RETURN LOSS (dB) -12 2x LO LO FREQUENCY (MHz) 26.5GHz 8 LO 3 2500 2450 2400 2350 2300 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VTUNE (V) -14 -30 -40 -16 -50 3x RF RBW = 1MHz 802.11g SIGNAL DC -60 -18 -70 -80 -20 2300 2350 2400 2450 2500 RF FREQUENCY (MHz) 2550 2600 -90 LO PHASE NOISE vs. OFFSET FREQUENCY -60 -70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 -150 0.001 -50kHz 0.01 0.1 1 OFFSET FREQUENCY (MHz) 10 10kHz/ div MAX2830 toc48 CHANNEL SWITCHING FREQUENCY SETTLING (FROM 2500MHz TO 2400MHz) 50kHz MAX2830 toc49 -50 0 250s PLL SETTLING TIME FROM SHUTDOWN TO STANDBY MODE 50kHz MAX2830 toc50 PLL SETTLING TIME FROM STANDBY TO Tx 50kHz MAX2830 toc51 10kHz/ div 10kHz/ div -50kHz 0 2ms -50kHz 0 30s 16 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Typical Operating Characteristics (continued) (MAX2830 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.) Rx-TO-Tx TURNAROUND PLL SETTLING TIME 25kHz MAX2830 toc52 MAX2830 Tx-Rx TURNAROUND PLL SETTLING TIME 25kHz MAX2830 toc53 5kHz/ div 5kHz/div -25kHz 0 50s -25kHz 0 50s CLOCK OUTPUT MAX2830 toc54 CRYSTAL-OSCILLATOR OFFSET FREQUENCY vs. CRYSTAL-OSCILLATOR TUNING BITS 800 700 600 500 400 300 200 100 0 -100 -200 -300 -400 -500 -600 -700 -800 KYOCERA (CX-3225SB) MAX2830 toc55 3V 0V 10ns/div CRYSTAL OFFSET FREQUENCY (Hz) fCLOCK = 40MHz CLOAD = 5pF 0 10 20 30 40 50 60 70 80 90 100110120130 CTUNE (DIGITAL BITS) ______________________________________________________________________________________ 17 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Block Diagram/Typical Operating Circuit MODE CONTROL TX INPUT RX BASEBAND HPF CORNER FREQUENCY CONTROL RX I OUTPUTS VCCRXFL TXBBQ+ TXBBQ- VCCRXVGA ANTSEL VCCRXMX RXBBI+ 38 TXBBI+ TXBBI- 48 VCCLNA GNDRXLNA 1 47 46 45 44 43 42 41 40 39 RXBBI37 36 MUX RXBBQ+ RXBBQB4 BYPASS TUNE GNDVCO VCCVCO CTUNE XTAL VCCXTAL GNDCP VCCCP RX Q OUTPUTS RX/TX GAIN CONTROL 2 3 4 5 6 7 8 9 10 Rx/Tx ANTENNA SWITCH MAX2830 RSSI RXHP RXTX RX INPUT RX/TX GAIN CONTROL B6 ANT1+ ANT1- TO RSSI MUX 35 MUX 34 33 32 31 PLL 30 29 28 27 26 90 IMUX QMUX 0 RX GAIN CONTROL B7 VCCPA TX OUTPUT RX/TX GAIN CONTROL B3 ANT2+ ANT2- AM DETECTOR %1,2 TEMP SENSOR TO RSSI MUX POWER DETECTOR CRYSTAL OSCILLATOR/ BUFFER RX/TX GAIN CONTROL MODE CONTROL B2 11 SHDN 12 TEMP SENSOR RSSI 13 14 RSSI MUX 15 16 17 SERIAL INTERFACE %1,2 25 22 23 24 18 19 20 21 B5 B1 CLOCKOUT VCCTXPA RX/TX GAIN CONTROL VCCTXMX SERIAL INPUTS REFERENCE CLOCK BUFFER OUTPUT RX/TX GAIN CONTROL NOTE: ALL GROUND PINS (PINS 2, 26, AND 31) AND BYPASS CAPACITORS' GROUND REQUIRE THEIR OWN VIAS TO GROUND. DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND. 18 ______________________________________________________________________________________ CPOUT SCLK RSSI DIN VCCPLL CS LD 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NAME VCCLNA GNDRXLNA B6 ANT1+ ANT1B7 VCCPA B3 ANT2+ ANT2B2 SHDN VCCTXPA B5 CS RSSI VCCTXMX SCLK DIN VCCPLL CLOCKOUT LD B1 CPOUT VCCCP GNDCP VCCXTAL XTAL CTUNE VCCVCO GNDVCO TUNE BYPASS B4 LNA Supply Voltage LNA Ground Receiver and Transmitter Gain-Control Logic-Input Bit 6 Antenna 1. Differential Input to LNA in Rx mode. Input is internally AC-coupled and matched to 100 differential. Connect directly to a 2:1 balun. Receiver Gain-Control Logic-Input Bit 7 Supply Voltage for Second Stage of Power Amplifier Receiver and Transmitter Gain-Control Logic-Input Bit 3 Antenna 2. Differential inputs to LNA in diversity Rx mode and to PA differential outputs in Tx mode. Internally AC-coupled differential outputs and matched to 100 differential. Connect directly to a 2:1 balun. Receiver and Transmitter Gain-Control Logic-Input Bit 2 Active-Low Shutdown and Standby Logic Input. See Table 32 for operating modes. Supply Voltage for First-Stage of PA and PA Driver Receiver and Transmitter Gain-Control Logic-Input Bit 5 Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (see Figure 3) RSSI, PA Power Detector or Temperature-Sensor Multiplexed Analog Output Transmitter Upconverter Supply Voltage Serial-Clock Logic Input of 3-Wire Serial Interface (see Figure 3) Data Logic Input of 3-Wire Serial Interface (see Figure 3) PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings. Reference Clock Buffer Output Lock-Detect Logic Output of Frequency Synthesizer. Output high indicates that the frequency synthesizer is locked. Output programmable as CMOS or open-drain output. (See Tables 17 and 21.) Receiver and Transmitter Gain-Control Logic-Input Bit 1 Charge-Pump Output. Connect the frequency synthesizer's loop filter between CPOUT and TUNE (see the Block Diagram/Typical Operating Circuit). PLL Charge-Pump Supply Voltage Charge-Pump Circuit Ground Crystal Oscillator Supply Voltage Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input. Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input, leave CTUNE unconnected. VCO Supply Voltage VCO Ground VCO TUNE Input (see the Block Diagram/Typical Operating Circuit) On-Chip VCO Regulator Output Bypass. Bypass with a 0.1F to 1F capacitor to GND. Do not connect other circuitry to this point. Receiver and Transmitter Gain-Control Logic-Input Bit 4 FUNCTION MAX2830 ______________________________________________________________________________________ 19 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Pin Description (continued) PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 EP NAME RXBBQRXBBQ+ RXBBIRXBBI+ VCCRXVGA RXHP VCCRXFL TXBBQTXBBQ+ TXBBITXBBI+ VCCRXMX ANTSEL RXTX EP FUNCTION Receiver Baseband Q-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage and sideband detector outputs. Receiver Baseband I-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage and sideband detector outputs. Receiver VGA Supply Voltage Receiver Baseband AC-Coupling High-Pass Corner Frequency Control Logic Input Receiver Baseband Filter Supply Voltage Transmitter Baseband I-Channel Differential Inputs Transmitter Baseband Q-Channel Differential Inputs Receiver Downconverters Supply Voltage Antenna Selection Logic Input. See Table 1 for operation Rx/Tx Mode Control Logic Input. See Table 32 for operating modes. Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat dissipation. Do not share with any other pin grounds and bypass capacitors' ground. Detailed Description The MAX2830 single-chip, low-power, direct conversion, zero-IF transceiver is designed to support 802.11g/b applications operating in the 2.4GHz to 2.5GHz band. The fully integrated transceivers include a receive path, transmit path, VCO, sigma-delta fractional-N synthesizer, crystal oscillator, RSSI, PA power detector, temperature sensor, Rx and Tx I/Q error-detection circuitry, basebandcontrol interface, linear power amplifier, and an Rx/Tx antenna diversity switch. The only additional components required to implement a complete radio front-end solution are a crystal, a pair of baluns, a BPF, and a small number of passive components (RCs, no inductors required). MAX2830 2 2 ANT1 2 2 ANT2 2 LNA Rx/Tx and Antenna Diversity Switches The MAX2830 integrates an Rx/Tx switch and an antenna diversity switch before the receiver and after the power amplifier. See Figure 1 for a block diagram of the switches. The receiver and transmitter enable pin (RXTX) and the antenna selection pin (ANTSEL) determine which ports (ANT1 or ANT2) the receiver or transmitter is connected to. See Table 1 for the Rx/Tx and antenna diversity switches truth table. When RXTX = 0 PA Figure 1. Simplified Rx/Tx and Antenna Diversity Switch Structure (receive mode) and ANTSEL = 0, the switch provides a low-insertion loss path (main) between the ANT1 port (pins 4 and 5) and the receiver. When RXTX = 0 (receive mode) and ANTSEL = 1, the switch provides Table 1. Rx/Tx and Antenna Diversity Switches Operation RXTX 0 0 1 ANTSEL 0 1 X MODE Rx (main) Rx (diversity) Tx ANTENNA Ant1_ Ant2_ Ant2_ 20 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch an antenna diversity path between the ANT2 port (pins 9 and 10) and the receiver. When RXTX = 1, the PA and transmit path are automatically connected to the ANT2 port, regardless of the logic state of ANTSEL. For solutions not requiring antenna diversity, set ANTSEL logic-level high, enabling only the ANT2 port for both receive and transmit modes. The ANT1 and ANT2 differential ports are internally ACcoupled and internally matched to 100. Directly connect 2:1 baluns or balanced bandpass filters (BPFs) to these ports for applications requiring antenna diversity. For applications not requiring antenna diversity, only a single balun or balanced BPF is required on the ANT2 port, and the ANT1 port can be left open. Provide electrically symmetrical input traces to the baluns to maintain IP2 and RF common-mode noise rejection for the receiver, and to maintain a balanced load for the PA. interface by programming bits D6:D5 in Register 11 (A3:A0 = 1011) or programmed in parallel through the digital logic gain-control pins, B7 (pin 6) and B6 (pin 3). Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable programming through the SPI interface, or set bit D12 = 0 to enable parallel programming. See Table 2 for LNA gain-control settings. MAX2830 Receiver After the switch, the receiver integrates an LNA and VGA with a 95dB digitally programmable gain control range, direct-conversion downconverters, I/Q baseband lowpass filters with programmable LPF corner frequencies, analog RSSI and integrated DC-offset correction circuitry. A logic-low on the RXTX input (pin 48) and a logic-high on the SHDN input (pin 12) enable the receiver. Baseband Variable-Gain Amplifier The receiver baseband variable-gain amplifiers provide 62dB of gain control range programmable in 2dB steps. The VGA gain can be serially programmed through the SPI interface by setting bits D4:D0 in Register 11 (A3:A0 = 1011) or programmed in parallel through the digital logic gain-control pins, B5 (pin 14), B4 (pin 34), B3 (pin 8), B2 (pin 11), and B1 (pin 23). Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable serial programming through the serial interface or set bit D12 = 0 to enable parallel programming through the external logic pins. See Table 3 for the gain-step value and Table 4 for baseband VGA gain-control settings. Receiver Baseband Lowpass Filter The receiver integrates lowpass filters that provide an upper -3dB corner frequency of 8.5MHz (nominal mode) with 50dB of attenuation at 20MHz, and 45ns of group delay ripple in the passband (10kHz to 8.5MHz). The upper -3dB corner frequency is tightly controlled on-chip and does not require user adjustment. However, provisions are made to allow fine tuning of the upper -3dB LNA Gain Control The LNA has three gain modes: max gain, max gain -16dB, and max gain -33dB. The three LNA gain modes can be serially programmed through the SPITM Table 2. LNA Gain-Control Settings (Pins B7:B6 or Register A3:A0 = 1011, D6:D5) B7 OR D6 1 1 0 B6 OR D5 1 0 X NAME High Medium Low DESCRIPTION Max gain Max gain - 16dB (typ) Max gain - 33dB (typ) Table 4. Baseband VGA Gain-Control Settings in Receiver Gain-Control Register (Pin B5:B1 or Register D4:D0, A3:A0 = 1011) B5:B1 OR D4:D0 11111 11110 11101 : 00000 GAIN Max Max - 2dB Max - 4dB : Min Table 3. Receiver Baseband VGA GainStep Value (Pins B5:B1 or Register D4:D0, A3:A0 = 1011) PIN/BIT B1/D0 B2/D1 B3/D2 B4/D3 B5/D4 GAIN STEP (dB) 2 4 8 16 32 Table 5. Receiver LPF Coarse -3dB Corner Frequency Settings in Register (A3:A0 = 1000) BITS (D1:D0) 00 01 10 11 -3dB CORNER FREQUENCY (MHz) 7.5 8.5 15 18 MODE 11b 11g Turbo 1 Turbo 2 SPI is a trademark of Motorola, Inc. ______________________________________________________________________________________ 21 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 corner frequency. In addition, coarse frequency tuning allows the -3dB corner frequency to be set to 7.5MHz (11b mode), 8.5MHz (11g mode), 15MHz (turbo 1 mode), and 18MHz (turbo 2 mode) by programming bits D1:D0 in Register 8 (A3:A0 = 1000). See Table 3. The coarse corner frequency can be fine-tuned approximately 10% in 5% steps by programming bits D2:D0 in Register 7 (A3:A0 = 0111). See Table 6 for receiver LPF fine -3dB corner frequency adjustment. Baseband Highpass Filter and DC Offset Correction The receiver implements programmable AC and nearDC coupling of I/Q baseband signals. Temporary ACcoupling is used to quickly remove LO leakage and other DC offsets that could saturate the receiver outputs. When DC offsets have settled, near DC-coupling is enabled to avoid attenuation of the received signal. AC-coupling is set (-3dB highpass corner frequency of 600kHz) when a logic-high is applied to RXHP (pin 40). Near DC-coupling is set (-3dB highpass corner frequency of 100Hz nominal) when a logic-low is applied to RXHP. Bits D13:D12 in Register 7 (A3:A0 = 0111) allow the near DC-coupling -3B highpass corner frequency to be set to 100Hz (D13:D12 = 00), 4kHz (D13:D12 = X1), or 30kHz (D13:D12 = 10). See Table 7. Receiver I/Q Baseband Outputs The differential outputs (RXBBI+, RXBBI-, RXBBQ+, RXBBQ-) of the baseband amplifiers have a differential output impedance of ~300, and are capable of driving differential loads up to 10k || 10pF. The outputs are internally biased to a common-mode voltage of 1.2V and are intended to be DC-coupled to the inphase (I) and quadrature (Q) analog-to-digital data converter inputs of the accompanying baseband IC. Additionally, the common-mode output voltage can be adjusted from 1.2V to 1.5V through programming bits D11:D10 in Register 15 (A3:A0 = 1111). Received Signal-Strength Indicator (RSSI) The RSSI output (pin 16) can be programmed to multiplex an analog output voltage proportional to the received signal strength, the PA output power, or the die temperature. Set bits D9:D8 = 00 in Register 8 (A3:A0 = 1000) to enable the RSSI output in receive mode (off in transmit mode). Set bit D10 = 1 to enable the RSSI output when RXHP = 1, and disable the RSSI output when RXHP = 0. Set bit D10 = 0 to enable the RSSI output independent of RXHP. See Table 8 for a summary of the RSSI output vs. register programming and RXHP. The RSSI provides an analog voltage proportional to the log of the sum of the squares of the I and Q channels, measured after the receive baseband filters and before the variable-gain amplifiers. The RSSI analog output voltage is proportional to the RF input signal level and LNA gain state over a 60dB range, and is not dependent upon VGA gain. See the Rx RSSI Output vs. Input Power graph in the Typical Operating Characteristics for further details. Table 6. Receiver LPF Fine -3dB Corner Frequency Adjustment in Register (A3:A0 = 0111) BITS (D2:D0) 000 001 010 011 100 % ADJUSTMENT RELATIVE TO COARSE SETTING 90 95 100 105 110 Table 8. RSSI Pin Truth Table INPUT CONDITIONS A3:A0 = 1000, D9:D8 X 00 01 10 00 01 10 A3:A0 = 1000, D10 0 0 0 0 1 1 1 RXHP 0 1 1 1 X X X RSSI OUTPUT No signal RSSI Temperature sensor Power detector RSSI Temperature sensor Power detector Table 7. Receiver Highpass Filter -3dB Corner Frequency Programming RXHP 1 0 0 0 A3:A0 = 0111, D13:D12 XX 00 X1 10 -3dB HIGHPASS CORNER FREQUENCY (Hz) 600k 100 (recommended) 4k 30k X = Don't care. X = Don't care. 22 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Transmitter The transmitter integrates baseband lowpass filters, direct-upconversion mixers, a VGA, a PA driver, and a linear RF PA with a power detector. A logic-high on the RXTX input (pin 48) and a logic-high on the SHDN input (pin 12) enable the transmitter. The PA outputs are routed to ANT2, regardless of the state at ANTSEL. Register 8 (A3:A0 = 1000) and bit D5:D3 in Register 7 (A3:A0 = 0111). The -3dB corner frequency is tightly controlled on-chip and does not require user adjustment. Additionally, provisions are made to fine tune the -3dB corner frequency through bits D5:D3 in the Filter Programming register (A3:A0 = 0111). See Tables 9 and 10. MAX2830 Transmitter I/Q Baseband Inputs The differential analog inputs of the transmitter baseband amplifier I/Q inputs (TXBBI+, TXBBI-, TXBBQ+, TXBBQ-) have a differential impedance of 20k || 1pF. The inputs require an input common-mode voltage of 0.9V to 1.3V, which is provided by the DC-coupled I and Q DAC outputs of the accompanying baseband IC. Transmitter Baseband Lowpass Filtering The transmitter integrates lowpass filters that can be tuned to -3dB corner frequencies of 8MHz (11b), 11MHz (11g), 16.5MHz (turbo 1 mode), and 22.5MHz (turbo 2 mode) through programming bits D1:D0 in Transmitter Variable-Gain Amplifier The variable-gain amplifier of the transmitter provides 31dB of gain control range programmable in 0.5dB steps over the top 8dB of the gain control range and in 1dB steps below that. The transmitter gain can be programmed serially through the SPI interface by setting bits D5:D0 in Register 12 (A3:A0 = 1100) or in parallel through the digital logic gain-control pins B6:B1 (pins 3, 6, 8, 11, 14, 23, and 34, respectively). Set bit D10 = 0 in Register 9 (A3:A0 = 1001) to enable parallel programming, and set bit D10 = 1 to enable programming through the 3-wire serial interface. See Table 11 for the transmitter VGA gain-control settings. Table 9. Transmitter LPF Coarse -3dB Corner Frequency Settings in Register (A3:A0 = 1000) BITS (D1:D0) 00 01 10 11 -3dB CORNER FREQUENCY (MHz) 8 11 16.5 22.5 MODE 11b 11g Turbo 1 Turbo 2 Table 11. Transmitter VGA Gain-Control Settings NO. 63 62 61 : 49 48 47 46 45 44 : 5 4 3 2 1 0 D5:D0 OR B6:B1 111111 111110 111101 : 110001 110000 101111 101110 101101 101100 : 000101 000100 000011 000010 000001 000000 OUTPUT SIGNAL POWER Max Max - 0.5dB Max - 1.0dB : Max - 7dB Max - 7.5dB Max - 8dB Max - 8dB Max - 9dB Max - 9dB : Max - 29dB Max - 29dB Max - 30dB Max - 30dB Max - 31dB Max - 31dB Table 10. Transmitter LPF Fine -3dB Corner Frequency Adjustment in Register (A3:A0 = 0111) BITS (D5:D3) 000 001 010 011 100 101 101-111 % ADJUSTMENT RELATIVE TO COARSE SETTING 90 95 100 105 110 (11g) 115 Not used ______________________________________________________________________________________ 23 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Power-Amplifier Bias and Enable Delay The MAX2830 integrates a 2-stage PA, providing +17.1dBm of output power at 5.6% error vector magnitude (EVM) (54Mbps OFDM signal) in 802.11g mode while exceeding the 802.11g spectral mask requirements. The first and second stage PA bias currents are set through programming bits D2:D0 and bits D6:D3 in Register 10 (A3:A0 = 1010), respectively. An adjustable PA enable delay, relative to the transmitter enable (RXTX low-to-high transition), can be set from 200ns to 7s through programming bits D13:D10 in Register 10 (A3:A0 = 1010). Power Detector The MAX2830 integrates a voltage-peak detector at the PA output and before the switch to provide an analog voltage proportional to PA output power. See the Power Detector over Frequency and Power Detector over Supply Voltage graphs in the Typical Operating Characteristics. Set bits D9:D8 = 10 in Register 8 (A3:A0 = 1000) to multiplex the power-detector analog output voltage to the RSSI output (pin 16). 1 or a divide-by-2 reference frequency divider, an 8-bit integer portion main divider with a divisor range programmable from 64 to 255, and a 20-bit fractional portion main-divider. Bit D2 in Register 5 (A3:A0 = 0101) sets the reference oscillator divider ratio to 1 or 2. Bits D7:D0 in Register 3 (A3:A0 = 0011) set the integer portion of the main divider. The 20-bit fractional portion of the main-divider is split between two registers. The 14 MSBs of the fractional portion are set in Register 4 (A3:A0 = 0100), and the 6 LSBs of the fractional portion of the main divider are set in Register 3 (A3:A0 = 0011). See Tables 12 and 13. MAX2830 Synthesizer Programming The MAX2830 integrates a 20-bit sigma-delta fractionalN synthesizer, allowing the device to achieve excellent phase-noise performance (0.9 RMS from 10kHz to 10MHz), fast PLL settling times, and an RF frequency step-size of 20Hz. The synthesizer includes a divide-by- Calculating Integer and Fractional Divider Ratios The desired integer and fractional divider ratios can be calculated by dividing the RF frequency (fRF) by fCOMP. For nominal 802.11g/b operation, a 40MHz reference oscillator is divided by 2 to generate a 20MHz comparison frequency (fCOMP). The following method can be used when calculating divider ratios supporting various reference and comparison frequencies: LO Frequency Divider = fRF / fCOMP = 2437MHz / 20MHz = 121.85 Integer Divider = 121 (d) = 0111 1001 (binary) Fractional Divider = 0.85 x (220 - 1) = 891289 (decimal) = 1101 1001 1001 1001 1001 See Table 14 for integer and fractional divider ratios for 802.11g/b systems using a 20MHz comparison frequency. Table 12. Integer Divider Register (A3:A0 = 0011) BIT D13:D8 D7:D0 RECOMMENDED 000000 01111001 DESCRIPTION 6 LSBs of 20-Bit Fractional Portion of Main Divider 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255. Table 13. Fractional Divider Register (A3:A0 = 0100) BIT D13:D0 RECOMMENDED 11011001100110 DESCRIPTION 14 MSBs of 20-Bit Fractional Portion of Main Divider 24 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Table 14. IEEE 802.11g/b Divider-Ratio Programming Words fRF (MHz) 2412 2417 2422 2427 2432 2437 2442 2447 2452 2457 2462 2467 2472 2484 (fRF / fCOMP) 120.6 120.85 121.1 121.35 121.6 121.85 122.1 122.35 122.6 122.85 123.1 123.35 123.6 124.2 INTEGER DIVIDER A3:A0 = 0011, D7:D0 0111 1000b 0111 1000b 0111 1001b 0111 1001b 0111 1001b 0111 1001b 0111 1010b 0111 1010b 0111 1010b 0111 1010b 0111 1011b 0111 1011b 0111 1011b 0111 1100b 2666h 3666h 0666h 1666h 2666h 3666h 0666h 1666h 2666h 3666h 0666h 1666h 2666h 0CCCh FRACTIONAL DIVIDER A3:A0 = 0100, D13:D0 A3:A0 = 0011, D13:D8 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 33h Crystal Oscillator The crystal oscillator has been optimized to work with low-cost crystals (e.g., Kyocera CX-3225SB). See Figure 2. The crystal oscillator frequency can be fine tuned through bits D6:D0 in Register 14 (A3:A0 = 1110), which control the value of CTUNE from 0.5pF to 15.4pF in 0.12pF steps. See the Crystal-Oscillator Offset Frequency vs. Crystal-Oscillator Tuning Bits graph in the Typical Operating Characteristics. The crystal oscillator can be used as a buffer for an external reference frequency source. In this case, the reference signal is ACcoupled to the XTAL pin, and capacitors C1 and C2 are not connected. When used as a buffer, the XTAL input pin has to be AC-coupled. The XTAL pin has an input impedance of 5k || 4pF, (set D6:D0 = 0000000 in Register 14 A3:A0 = 1110). Reference Clock Output Divider/Buffer The reference oscillator of the MAX2830 has a divider and a buffered output for routing the reference clock to the accompanying baseband IC. Bit D10 in Register 14 (A3:A0 = 1110) sets the buffer divider to divide by 1 or 2, independent of the divide ratio for the reference frequency provided to the PLL. Bit B9 in the same register enables or disables the reference buffer output. See the Clock Output waveform in the Typical Operating Characteristics. Loop Filter The PLL charge-pump output, CPOUT (pin 24), connects to an external third-order, lowpass RC loop-filter, which in turn connects to the voltage tuning input, TUNE (pin 32), of the VCO, completing the PLL loop. The charge-pump output sink and source current is 1mA, and the VCO tuning gain is 103MHz/V at 0.5V tune voltage and 86MHz/V at 2.2V tune voltage. The RC loop-filter values have been optimized for a loop bandwidth of 150kHz, to achieve the desired Rx/Tx turnaround settling time, while maintaining loop stability and good phase noise. Refer to the MAX2830 EV kit schematic for the recommended loop-filter component values. Keep the line from this pin to the tune input as short as possible to prevent spurious pickup. Lock-Detector Output The PLL features a logic lock-detect output. A logic-high indicates the PLL is locked, and a logic-low indicates the PLL is not locked. Bit D5 in Register 5 (A3:A0 = 0101) enables or disables the lock-detect output. Bit 25 MAX2830 XTAL C1 CTUNE 28 29 CTUNE 1.35k 5.9k C2 FOR EXTERNAL REFERENCE CLOCK SET, C1 = C2 = OPEN Figure 2. Crystal Oscillator Schematic ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 D12 in Register 1 (A3:A0 = 0001) configures the lockdetect output as a CMOS or open-drain output. In opendrain output mode, bit D9 in Register 5 (A3:A0 = 0101) enables or disables an internal 30k pullup resistor from the open-drain output. Register data is loaded through the 3-wire SPI/ MICROWIRETM-compatible serial interface. Data is shifted in MSB first and is framed by CS. When CS is low, the clock is active, and data is shifted with the rising edge of the clock. When CS transitions high, the shift register is latched into the register selected by the contents of the address bits. See Figure 3. Only the last 18 bits shifted into the device are retained in the shift register. No check is made on the number of clock pulses. For programming data words less than 14 bits long, only the required data bits and the address bits need to be shifted, resulting in faster Rx and Tx gain control where only the LSBs need to be programmed. Programmable Registers and 3-Wire SPI-Interface The MAX2830 includes 16 programmable, 18-bit registers. The 14 most significant bits (MSBs) are used for register data. The 4 least significant bits (LSBs) of each register contain the register address. See Table 15 for a summary of the registers and recommended register settings. Table 15. Recommended Register Settings* REGISTER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DATA D13 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 D12 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 D11 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 D10 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 D9 1 0 0 0 1 0 0 0 0 1 0 0 0 1 1 D8 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 D7 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 D6 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 D5 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 D4 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 D3 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 D2 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 D1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 D0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 ADDRESS (A3:A0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 TABLE 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 15 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1111 30 *The power-on register settings are not production tested. Recommended register settings must be loaded after VCC is supplied. DIN BIT 1 BIT 2 BIT 15 BIT 16 BIT 23 BIT 24 SCLK tCH tCL tCS1 tDS CS tCSO tCSS tDH tCSH tCSW Figure 3. 3-Wire SPI Serial-Interface Timing Diagram 26 MICROWIRE is a trademark of National Semiconductor Corp. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Table 16. Register 0 (A3:A0 = 0000) DATA BITS D13:D11 D10 D9:D0 RECOMMENDED 000 1 1101000000 Set to recommended value. Fractional-N PLL Mode Enable. Set 1 to enable the fractional-N PLL or set 0 to enable the integer-N PLL. Set to recommended value. DESCRIPTION Table 17. Register 1 (A3:A0 = 0001) DATA BITS D13 D12 D11:D0 RECOMMENDED 0 1 000110011010 Set to recommended value. Lock-Detector Output Select. Set to 1 for CMOS Output. Set to 0 for open-drain output. Bit D9 in register (A3:A0 = 0101) enables or disables an internal 30k pullup resistor in open-drain output mode. Set to recommended value. DESCRIPTION Table 18. Register 2 (A3:A0 = 0010) DATA BITS D13:D0 RECOMMENDED 01000000000011 Set to recommended value. DESCRIPTION This register contains the 8-bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer. Table 19. Register 3 (A3:A0 = 0011) BIT D13:D8 D7:D0 RECOMMENDED 00000 01111001 DESCRIPTION 6 LSBs of 20-Bit Fractional Portion of Main Divider 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255. Table 20. Register 4 (A3:A0 = 0100) BIT D13:D0 RECOMMENDED 11011001100110 DESCRIPTION 14 MSBs of 20-Bit Fractional Portion of Main Divider Table 21. Register 5 (A3:A0 = 0101) BIT D13:D10 D9 D8:D6 D5 D4:D3 D2 D1:D0 RECOMMENDED 0000 0 010 1 00 1 00 Set to recommended value. Lock-Detect Output Internal Pullup Resistor Enable. Set to 1 to enable internal 30k pullup resistor or set to 0 to disable the resistor. Only available when lock-detect, open-drain output is selected (A3:A0 = 0001, D12 = 1). Set to recommended value. Lock-Detect Output Enable. Set to 1 to enable the lock-detect output or set to 0 to disable the output. The output is high impedance when disabled. Set to recommended value. Reference Frequency Divider Ratio to PLL. Set to 0 to divide by 1. Set to 1 to divide by 2. Set to recommended value. DESCRIPTION ______________________________________________________________________________________ 27 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Table 22. Register 6 (A3:A0 = 0110) DATA BIT D13 D12:D11 D10:D7 D6 D5:D2 D1 D0 RECOMMENDED 0 00 0000 1 1000 0 0 Set to recommended value. Tx I/Q Calibration LO Leakage and Sideband Detector Gain-Control Bits. D12:D11 = 00: 9dB; 01 19dB; 10: 29dB; 11: 39dB. Set to recommended value. Power-Detector Enable in Tx Mode. Set to 1 to enable the power detector or set to 0 to disable the detector. Set to recommended value. Tx Calibration Mode. Set to 1 to place the device in Tx calibration mode or 0 to place the device in normal Tx mode when RXTX is set to 1 (see Table 32). Rx Calibration Mode. Set to 1 to place the device in Rx calibration mode or 0 to place the device in normal Rx mode when RXTX is set to 0 (see Table 32). DESCRIPTION Table 23. Register 7 (A3:A0 = 0111) BIT D13:D12 D11:D6 D5:D3 D2:D0 RECOMMENDED 01 000000 100 010 DESCRIPTION Receiver Highpass Corner Frequency Setting for RXHP = 0. Set to 00 for 100Hz, X1 for 4kHz, and 10 for 30kHz. Set to recommended value. Transmitter Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See Table 9. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment. Receiver Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See Table 6. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment. Table 24. Register 8 (A3:A0 = 1000) BIT D13 D12 D11 D10 RECOMMENDED 1 0 0 0 Set to recommended value. Enable Receiver Gain Programming Through the Serial Interface. Set to 1 to enable programming through the 3-wire serial interface (D6:D0 in Register A3:A0 = 1011). Set to 0 to enable programming in parallel through external digital pins (B7:B1). Set to recommended value. RSSI Operating Mode. Set to 1 to enable RSSI output independent of RXHP. Set to 0 to disable RSSI output if RXHP = 0, and enable the RSSI output if RXHP = 1. RSSI, Power Detector, or Temperature Sensor Output Select. Set to 00 to enable the RSSI output in receive mode. Set to 01 to enable the temperature sensor output in receive and transmit modes. Set to 10 to enable the power-detector output in transmit mode. See Table 7. Set to recommended value. Receiver and Transmitter Lowpass Filter Corner Frequency Coarse Adjustment. See Tables 4 and 7. DESCRIPTION D9:D8 D7:D2 D1:D0 00 001000 01 28 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Table 25. Register 9 (A3:A0 = 1001) BIT D13:D11 D10 D9:D0 RECOMMENDED 000 0 1110110101 Set to recommended value. Enable Transmitter Gain Programming Through the Serial or Parallel Interface. Set to 1 to enable programming through the 3-wire serial interface (D5:D0 in Register A3:A0 = 1011). Set to 0 to enable programming in parallel through external digital pins (B6:B1). Set to recommended value. DESCRIPTION Table 26. Register 10 (A3:A0 = 1010) BIT D13:D10 D9:D7 D6:D3 D2:D0 RECOMMENDED 0111 011 0100 100 DESCRIPTION Power-Amplifier Enable Delay. Sets a delay between RXTX low-to-high transition and internal PA enable. Programmable in 0.5s steps. D13:D10 = 0001 (0.2s) and D13:D10 = 1111 (7s). Set to recommended value. Second-Stage Power-Amplifier Bias Current Adjustment. Set to XXXX for 802.11g/b. First-Stage Power-Amplifier Bias Current Adjustment. Set to XXX for 802.11g/b. Table 27. Register 11 (A3:A0 = 1011) BIT D13:D7 D6:D5 D4:D0 RECOMMENDED 0000000 11 11111 Set to recommended value. LNA Gain Control. Set to 11 for high-gain mode. Set to 10 for medium-gain mode, reducing LNA gain by 16dB. Set to 0X for low-gain mode, reducing LNA gain by 33dB. Receiver VGA Control. Set D4:D0 = 00000 for minimum gain and D4:D0 = 11111 for maximum gain. DESCRIPTION Table 28. Register 12 (A3:A0 = 1100) BIT D13:D6 D5:D0 RECOMMENDED 00000101 000000 Set to recommended value. Transmitter VGA Gain Control. Set D5:D0 = 000000 for minimum gain, and set D5:D0 = 111111 for maximum gain. DESCRIPTION Table 29. Register 13 (A3:A0 = 1101) BIT D13:D10 D9:D6 D5:D0 RECOMMENDED 0011 1010 010010 Set to recommended value. Set to recommended value. Set to recommended value. DESCRIPTION ______________________________________________________________________________________ 29 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 Table 30. Register 14 (A3:A0 = 1110) BIT D13:D11 D10 D9 D8:D7 D6:D0 RECOMMENDED 000 0 1 10 XXXXXXX Set to recommended value. Reference Clock Output Divider Ratio. Set 1 to divide by 2 or set 0 to divide by 1. Reference Clock Output Enable. Set 1 to enable the reference clock output or set 0 to disable. Set to recommended value. Crystal-Oscillator Fine Tune. Tunes crystal oscillator over 20ppm to within 1ppm. DESCRIPTION X = Don't care. Table 31. Register 15 (A3:A0 = 1111) BIT D13:D12 D11:D10 D9:D0 RECOMMENDED 00 00 0101000101 Set to recommended value. Receiver I/Q Output Common-Mode Voltage Adjustment. Set D11:D10 = 00: 1.2V, 01: 1.3V, 10: 1.4V, 11: 1.5V. Set to recommended value. DESCRIPTION Table 32. Operating Mode Table LOGIC PINS MODE SHDN Shutdown Standby Rx Tx Rx Calibration Tx Calibration 0 0 1 1 1 1 RXTX 0 1 0 1 0 1 D1:D0 (A3:A0 = 0110) 00 00 X0 0X X1 1X Rx PATH Off Off On Off On (except LNA) Off Tx PATH Off Off Off On Upconverters On (except PA driver and PA) REGISTER SETTINGS CIRCUIT BLOCK STATES PLL, VCO, LO GEN, AUTOTUNER Off On On On On On CALIBRATION SECTIONS ON None None None None Cal tone, RF phase shift, Tx filter AM detector, Rx I/Q buffers X = Don't care. Note: See Table 1 for Rx/Tx and antenna diversity operating mode. Modes of Operation The modes of operation for the MAX2830 are shutdown, standby, transmit, receive, transmitter calibration, and receiver calibration. See Table 32 for a summary of the modes of operation. The logic-input pins, SHDN (pin 12) and RXTX (pin 48), control the various modes. loaded and values maintained, as long as V CC is applied. Set SHDN and RXTX logic-low to place the device in shutdown mode. Shutdown Mode The MAX2830 features a low-power shutdown mode that disables all circuit blocks, except the serial-interface and internal registers, allowing the registers to be 30 Standby Mode The standby mode is used to enable the frequency synthesizer block while the rest of the device is powered down. In this mode, the PLL, VCO, and LO generators are on, so that Tx or Rx modes can be quickly enabled from this mode. Set SHDN to a logic-low and RXTX to a logic-high to place the device in standby mode. ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Receive (Rx) Mode The complete receive signal path is enabled in this mode. Set SHDN to logic-high and RXTX to logic-low to place the device in Rx mode. Transmit (Tx) Mode The complete transmitter signal path is enabled in this mode. Set SHDN and RXTX to logic-high to place the device in Tx mode. Rx/Tx Calibration Mode The MAX2830 features Rx/Tx calibration modes to detect I/Q imbalances and transmit LO leakage. In the Tx calibration mode, all Tx circuit blocks, except the PA driver and external PA, are powered on and active. The AM detector and receiver I and Q channel buffers are also on, along with multiplexers in the receiver side to route this AM detector's signal. In this mode, the LO leakage calibration is done only for the LO leakage signal that is present at the center frequency of the channel (i.e., in the middle of the OFDM or QPSK spectrum). The LO leakage calibration includes the effect of all DC offsets in the entire baseband paths of the I/Q modulator and direct leakage of the LO to the I/Q modulator output. The LO leakage and sideband detector output are taken at the receiver I and Q channel outputs during this calibration phase. During Tx LO leakage and I/Q imbalance calibration, a sine and cosine signal (f = fTONE) is input to the baseband I/Q Tx pins from the baseband IC. At the LO leakage and sideband-detector output, the LO leakage corresponds to the signal at fTONE and the sideband suppression corresponds to the signal at 2 x fTONE. The output power of these signals vary 1dB for 1dB of variation in the LO leakage and sideband suppression. To calibrate the Tx path, first set the power-detector gain to 9dB using D12:D11 in Register 6 (see Table 22). Adjust the DC offset of the baseband inputs to minimize the signal at fTONE (LO leakage). Then, adjust the baseband input relative magnitude and phase offsets to reduce the signal at 2 x fTONE. In Rx calibration mode, the calibrated Tx RF signal is internally routed to the Rx inputs. In this mode, the VCO/LO generator/PLL blocks are powered on and active except for the low-noise amplifier (LNA). MAX2830 Applications Information Layout Issues The MAX2830 EV kit can be used as a starting point for layout. For best performance, take into consideration grounding and RF, baseband, and power-supply routing. Make connections from vias to the ground plane as short as possible. Do not connect the device ground pin to the exposed paddle ground. Keep the buffered clock output trace as short as possible. Do not share the trace with the RF input layer, especially on or interlayer or back side of the board. On the high-impedance ports, keep traces short to minimize shunt capacitance. EV kit Gerber files can be requested at www.maxim-ic.com. Power-Supply Layout To minimize coupling between different sections of the IC, a star power-supply routing configuration with a large decoupling capacitor at a central VCC node is recommended. The VCC traces branch out from this node, each going to a separate VCC node in the circuit. Place a bypass capacitor as close as possible to each supply pin. This arrangement provides local decoupling at each V CC pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Do not share the capacitor ground vias with any other branch and the exposed paddle ground. ______________________________________________________________________________________ 31 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch MAX2830 POWER SUPPLY ON POWER 3-WIRE SERIAL INTERFACE AVAILABLE IREF SHDN MAC SHUTDOWN RXTX MAX2830 CS MAC SPI SCLK DIN CS (SELECT) SCLK (CLOCK) DIN (DATA) SPI: CHANNEL FREQUENCY, PA BIAS, TRANSMITTER LINEARITY, RECEIVER RSSI OPERATION, CALIBRATION MODE, ETC. INTERNAL PA ENABLED 0 TO 7s RECEIVE MODE (DRIVES POWER RAMP CONTROL) SHUTDOWN MODE STANDBY MODE PA ENABLE TRANSMIT MODE Figure 4. Timing Diagram Pin Configuration VCCRXVGA VCCRXMX VCCRXFL TXBBQ+ Chip Information PROCESS: BiCMOS ANTSEL TXBBQ- RXBBI+ TXBBI+ RXHP RXTX TOP VIEW RXBBI- TXBBI- 48 47 46 45 44 43 42 41 40 39 38 37 VCCLNA GNDRXLNA B6 ANT1+ ANT1B7 VCCPA B3 ANT2+ ANT2B2 SHDN 1 2 3 4 5 6 7 8 9 10 11 12 EP* 13 14 15 16 17 18 19 20 21 22 23 24 VCCTXMX VCCPLL SCLK RSSI DIN CS CLOCKOUT LD B5 B1 VCCTXPA CPOUT + 36 RXBBQ+ 35 RXBBQ34 B4 33 BYPASS 32 TUNE Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 TQFN-EP PACKAGE CODE T4877+4 DOCUMENT NO. 21-0144 MAX2830 31 GNDVCO 30 VCCVCO 29 CTUNE 28 XTAL 27 VCCXTAL 26 GNDCP 25 VCCCP *EXPOSED PADDLE THIN QFN 32 ______________________________________________________________________________________ 2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA, and Rx/Tx/Antenna Diversity Switch Revision History REVISION NUMBER 0 1 REVISION DATE 3/07 7/09 Initial release Corrected Table 12 DESCRIPTION PAGES CHANGED -- 24 MAX2830 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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